MetalSlice refactors Apple Silicon SIMD execution from legacy thread-strided assignment into
cooperative SIMDgroups where 32 execution lanes collectively stream
32 lanes × 8 INT4 weights = 128 bytes (1 exact Apple Silicon cache line per step).
This eliminates the legacy G ≥ 128 SIMD lane starvation collapse,
where num_groups = K/G < 128 left 72%–86% of SIMD lanes idle.